1. Field of the Invention
The present invention relates generally to a method and apparatus for designing a large scale integrated circuit (LSI) for analog circuits. In particular, the present invention relates to a design technique which positions contact holes formed in an insulating layer on a master slice, prior to the connection of resistive cell regions in the master slice.
2. Description of the Related Art
Semiconductor integrated circuits designed and manufactured using the so-called master slice technique have circuit elements laid out on integrated circuit wafers in a way that optimizes the wiring or interconnection of the various circuit elements. The wiring done among circuit elements organized in this fashion is generally known as "personalization" or "customization".
A master slice is generally a silicon wafer containing 30 or more groups of components interconnected to form desired circuits. The components or elements of a master slice for an analog circuit may include, for example, bipolar transistor elements, capacitor elements, and resistive cell regions, formed in or on a semiconductor substrate. During personalization, an insulating layer is formed on the surface of the master slice. Thereafter, in order to use a part of a resistive cell region as a resistive element having a desired resistance, two contact holes are formed in the insulating layer over the resistive cell region. Contacts serving as interlayer wirings in the two holes connect the resistive cell region to wirings formed on the insulating layer. Formation of two contacts cause a part of the resistive cell region to be defined as a resistive element, with the resistance being determined by the spacing between the two contacts. Thus, during personalization of a master slice, various resistive elements can be defined by accurate positioning of the contact holes in the insulating layer.
Design techniques today used to develop digital gate arrays according to the Master Slice technique often incorporate a symbolic layout environment. Such an environment shortens the development period for digital LSI circuit design. A similar layout environment would also shorten the development period for designing analog LSI circuits.
In circuit layout design according to Master Slice Approach, a designer operates a pattern editor with reference to a desired circuit plan drawn on paper. In general, a pattern editor is built into a computer aided design (CAD) system having a display and an input device, e.g. a mouse interface. A bulk model of a master slice is displayed on the display screen, and represents parameters of the master slice such as bulk resistance, bulk noise, bulk modules as well as the transistance and capacitance of various regions formed in or on the semiconductor substrate.
The circuit layout designer specifies one element on the bulk model by operating the mouse or other input device. This effectively positions the element on the master slice. The designer then operates the input device to draw horizontal wiring patterns connecting the variously displayed elements. The wiring procedure is accomplished using contact patterns as vertical wirings to connect the horizontal wirings and terminals of the individual elements.
For example, as shown in FIG. 1A, a pair of contact hole patterns 91 and 92, spaced apart from each other by a distance L3, can be drawn above a resistive cell region 90 in a bulk model. Consequently, a part of the resistive cell region 90 can be used as a resistive element having a resistance determined by the distance L3. The designer is free to decide where the two contact hole patterns can be properly disposed within the resistive cell region 90. To do this, the designer must compute the length L3 by a manual operation or using a computer, based on the specified resistance values and parameters of the resistive cell region 90 (i.e. sheet resistance and the width of the cell region), shown in the circuit diagram. In other words, the designer must determine the contact hole spacing L3 in advance of his using the pattern editor.
During the wiring setting process, after the two contact hole patterns 91 and 92 have been positioned somewhere above the resistive cell region 90 as in FIG. 1A, it may turn out that a wiring 93, isolated from the first pattern 91, should preferably be placed where the first pattern 91 has been set. In this case, the first pattern 91 must be repositioned (or relocated) somewhere above the resistive cell region 90 in order to prevent it from overlapping the wiring pattern 93.
However, as long as the conventional pattern editor is used, the designer must operate the mouse or other input device such that the second pattern 92 is disposed at a position apart from the first pattern 91 by the spacing L3. This occurs after the reposition of the first pattern 91. Such a relocation operation is time consuming and troublesome for the designer. Furthermore, when a pattern has to be repositioned, the LSI design must once again undergo logical simulation to determine whether or not the mask patterns of the master slice conform to the circuit design. This is necessary to avoid circuit layout mistakes.
One method of defining a desired resistive element is to dispose a resistive element specifying pattern, integrated with two contact hole patterns, over the resistive cell region 90.
One disadvantage of this method, however, is that in order to adjust the relationship between the positions of two contact hole patterns and the position of a wiring pattern crossing the resistive element specifying pattern, the pattern library of the CAD system must store a plurality of resistive element specifying patterns having the same contact hole spacing, for example, a first resistive element specifying pattern such as that shown in FIG. 1B, in which two hole patterns 94 and 95 spaced apart from each other by a distance L3 are disposed in an approximately center of the resistive cell region 90, and a second resistive element specifying pattern such as that shown in FIG. 1C, in which two hole patterns 96 and 97 spaced apart from each other by a distance L3 are disposed closer to the right-hand end of the resistive cell region 90. A considerably large number of resistive element specifying patterns are required to account for instances of contact hole spacing representative of a single resistive value. Since many kinds of resistive elements and values are used in a single circuit design, the pattern library must store an enormously large number of resistive element specifying patterns. Consequently, the resistive element defining method requires a pattern library with a large storage capacity and a great deal of time and labor for preparing an enormously large number of patterns.